Recent advances in microfabrication techniques have fueled the growth trend of miniaturization of electronic devices. This device miniaturization trend is both a design and a fabrication challenge. Particularly, the physical design challenges associated at that scale are unprecedented.
Physical prototyping the early designs are time consuming and expensive. The complex interdependencies of electrical, thermal, and mechanical characteristics of the ICs are well documented. For example, the effects of voltage drop, and the subsequent temperature distribution of the die impacts the power integrity of the circuits. Further, given the nature of the packaging materials and the non-uniform temperature distribution, the differences in the coefficient of thermal expansion results in thermo-mechanical stresses affecting the reliability of the package itself due to debonding, fatigue, and warpage effects. Early identification and mitigation of these effects will result in significant performance and cost benefits.
Gaining comprehensive insights at that scale without oversimplification of the design is a serious simulation challenge. In this presentation, we propose a solution to this pressing problem using state-of-the-art FEA solver with a full 3D Flip Chip Ball Grid Array (BGA) package exposed to a loading condition called as Power Cycling with non-uniform temperature distribution on the die. In applications such as BGAs, the interconnections are made through solder balls and hence, the reliability of the package usually depends on the reliability of the solder itself. The model also accounts for the variations in material properties such as modulus of elasticity, coefficient of thermal expansion, and Poisson’s ratio as a function of temperature which allows for the calculation of the thermo-mechanical plastic strains within the solder joints. Further, the effects of ultra-low-k dielectric, typically implemented in flip-chips for better electrical performance, are accounted for with detailed substrate layer modelling. The presentation further describes the methods that have been developed to handle such complex simulations within OnScale’s efficient FEA solver deployed on a cloud HPC platform. The solver has been specifically developed to take advantage of the distributed memory resources available on the cloud using a fully distributed MPI communication to achieve close to linear speed-up over thousands of compute nodes. The nature of the distributed architecture allows for hundreds of multi-variable optimization studies with high fidelity resulting in huge savings in time and cost.